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? semiconductor components industries, llc, 2007 january, 2007 ? rev. 10 1 publication order number: ncp5314/d ncp5314 two/three/four?phase buck cpu controller the ncp5314 provides full?featured and flexible control for the latest high?performance cpus. the ic can be programmed as a two?, three? or four?phase buck controller, and the per?phase switching frequency can be as high as 1.2 mhz. combined with external gate drivers and power components, the controller implements a compact, highly integrated multi?phase buck converter. enhanced v 2 ? control inherently compensates for variations in both line and load, and achieves current sharing between phases. this control scheme provides the industry?s fastest transient response, reducing the need for large banks of output capacitors and higher switching frequency. the controller meets vr(m)10.x specifications with all the required functions and protection features. features ? switching regulator controller ? programmable 2/3/4 phase operation ? lossless current sensing ? enhanced v 2 control method provides fast transient response ? programmable up to 1.2 mhz switching frequency per phase ? 0 to 100% adjustment of duty cycle ? programmable adaptive voltage positioning reduces output capacitor requirements ? programmable soft?start ? current sharing ? differential current sense pins for each phase ? current sharing within 10% between phases ? protection features ? programmable pulse?by?pulse current limit for each phase ? ?111110? and ?1 11111? dac code fault ? latching off overvoltage protection ? programmable latching overcurrent protection ? undervoltage lockout ? external enable control ? three?state mosfet driver control through driver?on signal ? system power management ? 6?bit dac with 0.5% tolerance compatible with vr(m)10.x specification ? programmable lower power good threshold ? power good output ? pb?free package is available http://onsemi.com a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package marking diagrams 32 pin qfn mn suffix case 485j (bottom view) 32 ncp5314 awlyyww 1 lqfp?32 ftb suffix case 873a ncp5314 awlyywwg 32 1 i lim r osc v cc gate1 gate2 gate3 gate4 gnd v id2 v id3 v id4 pwrls v ffb ss pwrgd drvon 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 v id1 v id0 v id5 enable cs2n cs2p cs1n cs1p sgnd v drp v fb comp cs4n cs4p cs3n cs3p pin connections device package shipping ? ordering information ncp5314mnr2 32 pin qfn 2500 tape & ree l 2000 tape & ree l ncp5314ftr2 lqfp?32 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 2000 tape & ree l ncp5314ftr2g lqfp?32 (pb?free)
ncp5314 http://onsemi.com 2 figure 1. application diagram, 12 v to 0.8 v ? 1.6 v, four?phase converter v id2 v id3 v id4 pwrls v ffb ss pwrgd drvon i lim r osc v cc gate1 gate2 gate3 gate4 gnd v id1 v id0 v id5 enable cs2n cs2p cs1n cs1p sgnd v drp v fb comp cs4n cs4p cs3n cs3p 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 pwrgd 3.3 v v id4 v id3 v id2 v id1 v id0 v id5 enable 3.3 v v s co en pgnd bst tg drn bg ncp5355 3 2 1 7 6 4 5 8 12 v atx 12 v v s co en pgnd bst tg drn bg ncp5355 3 2 1 7 6 4 5 8 v s co en pgnd bst tg drn bg ncp5355 3 2 1 7 6 4 5 8 v s co en pgnd bst tg drn bg ncp5355 3 2 1 7 6 4 5 8 + + v core gnd sgnd near socket v ffb connection ncp5314 r fb 1.5 k typ 1.5 k typ r1 r2 r drp c amp c ss l in c in l 01 l 02 l 03 l 04 c out r cs1 c cs1 c cs2 r cs2 r osc1 r osc2 r cs3 r cs4 c cs4 c cs3
ncp5314 http://onsemi.com 3 maximum ratings rating value unit operating junction temperature 150 c lead temperature soldering, reflow (note 1) 230 peak c storage temperature range ?65 to 150 c esd susceptibility: human body model 2.0 kv jedec moisture sensitivity level (msl): lqfp qfn 1 2 ? ? package thermal resistance: r ja lqfp qfn, pad soldered to pcb 52 34 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 60 second maximum above 183 c. maximum ratings pin number pin symbol v max v min i source i sink 1?3, 30?32 v id0 ?v id5 18 v ?0.3 v 1.0 ma 1.0 ma 4 pwrgds 7.0 v ?0.3 v 1.0 ma 1.0 ma 5 v ffb 7.0 v ?0.3 v 1.0 ma 1.0 ma 6 ss 7.0 v ?0.3 v 1.0 ma 1.0 ma 7 pwrgd 18 v ?0.3 v 1.0 ma 20 ma 8 drvon 7.0 v ?0.3 v 1.0 ma 1.0 ma 9 sgnd 1.0 v ?1.0 v 1.0 ma ? 10 v drp 7.0 v ?0.3 v 1.0 ma 1.0 ma 11 v fb 7.0 v ?0.3 v 1.0 ma 1.0 ma 12 comp 7.0 v ?0.3 v 1.0 ma 1.0 ma 13 cs4n 18 v ?0.3 v 1.0 ma 1.0 ma 14 cs4p 18 v ?0.3 v 1.0 ma 1.0 ma 15 cs3n 18 v ?0.3 v 1.0 ma 1.0 ma 16 cs3p 18 v ?0.3 v 1.0 ma 1.0 ma 17 gnd ? ? 0.4 a, 1.0 s, 100 ma dc ? 18?21 gate4?gate1 18 v ?0.3 v 0.1 a, 1.0 s, 25 ma dc 0.1 a, 1.0 s, 25 ma dc 22 v cc 18 v ?0.3 v ? 0.4 a, 1.0 s, 100 ma dc 23 r osc 7.0 v ?0.3 v 1.0 ma 1.0 ma 24 i lim 7.0 v ?0.3 v 1.0 ma 1.0 ma 25 cs1p 18 v ?0.3 v 1.0 ma 1.0 ma 26 cs1n 18 v ?0.3 v 1.0 ma 1.0 ma 27 cs2p 18 v ?0.3 v 1.0 ma 1.0 ma 28 cs2n 18 v ?0.3 v 1.0 ma 1.0 ma 29 enable 18 v ?0.3 v 1.0 ma 1.0 ma
ncp5314 http://onsemi.com 4 electrical characteristics (0 c < t a < 70 c; v cc = 12 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 32.4 k , v(i lim ) = 1.0 v, dac code 010100; unless otherwise noted) voltage identification (vid) voltage identification dac (0 = connected to gnd, 1 = open or pull?up to internal 3.3 v or external 5 v) min typ max unit v id code* (v) v out no load? (v) accuracy v id code (all codes) connect v fb to cond, measure comp ?0.5 ? +0.5% % v id4 v id3 v id2 v id1 v id0 v id5 0 1 0 1 0 0 0.8375 0.8134 0.8175 0.8216 v 0 1 0 0 1 1 0.8500 0.8259 0.8300 0.8342 v 0 1 0 0 1 0 0.8625 0.8383 0.8425 0.8467 v 0 1 0 0 0 1 0.8750 0.8507 0.8550 0.8593 v 0 1 0 0 0 0 0.8875 0.8632 0.8675 0.8718 v 0 0 1 1 1 1 0.9000 0.8756 0.8800 0.8844 v 0 0 1 1 1 0 0.9125 0.8880 0.8925 0.8970 v 0 0 1 1 0 1 0.9250 0.9005 0.9050 0.9095 v 0 0 1 1 0 0 0.9375 0.9129 0.9175 0.9221 v 0 0 1 0 1 1 0.9500 0.9254 0.9300 0.9347 v 0 0 1 0 1 0 0.9625 0.9378 0.9425 0.9472 v 0 0 1 0 0 1 0.9750 0.9502 0.9550 0.9598 v 0 0 1 0 0 0 0.9875 0.9627 0.9675 0.9723 v 0 0 0 1 1 1 1.0000 0.9751 0.9800 0.9849 v 0 0 0 1 1 0 1.0125 0.9875 0.9925 0.9975 v 0 0 0 1 0 1 1.0250 1.0000 1.0050 1.0100 v 0 0 0 1 0 0 1.0375 1.0124 1.0175 1.0226 v 0 0 0 0 1 1 1.0500 1.0249 1.0300 1.0352 v 0 0 0 0 1 0 1.0625 1.0373 1.0425 1.0477 v 0 0 0 0 0 1 1.0750 1.0497 1.0550 1.0603 v 0 0 0 0 0 0 1.0875 1.0622 1.0675 1.0728 v 1 1 1 1 1 1 off v 1 1 1 1 1 0 off v 1 1 1 1 0 1 1.1000 1.0746 1.0800 1.0854 v 1 1 1 1 0 0 1.1125 1.0870 1.0925 1.0980 v 1 1 1 0 1 1 1.1250 1.0995 1.1050 1.1105 v 1 1 1 0 1 0 1.1375 1.1119 1.1175 1.1231 v 1 1 1 0 0 1 1.1500 1.1244 1.1300 1.1357 v 1 1 1 0 0 0 1.1625 1.1368 1.1425 1.1482 v 1 1 0 1 1 1 1.1750 1.1492 1.1550 1.1608 v 1 1 0 1 1 0 1.1875 1.1617 1.1675 1.1733 v 1 1 0 1 0 1 1.2000 1.1741 1.1800 1.1859 v 1 1 0 1 0 0 1.2125 1.1865 1.1925 1.1985 v 1 1 0 0 1 1 1.2250 1.1990 1.2050 1.2110 v *vid code is for reference only. ?v out no load is the input to the error amplifier.
ncp5314 http://onsemi.com 5 electrical characteristics (0 c < t a < 70 c; v cc = 12 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 32.4 k , v(i lim ) = 1.0 v, dac code 010100; unless otherwise noted) voltage identification (vid) (continued) voltage identification dac (0 = connected to gnd, 1 = open or pull?up to internal 3.3 v or external 5 v) min typ max unit v id code* (v) v out no load? (v) accuracy v id code (all codes) connect v fb to cond, measure comp ?0.5 ? +0.5% % v id4 v id3 v id2 v id1 v id0 v id5 1 1 0 0 1 0 1.2375 1.2114 1.2175 1.2236 v 1 1 0 0 0 1 1.2500 1.2239 1.2300 1.2362 v 1 1 0 0 0 0 1.2625 1.2363 1.2425 1.2487 v 1 0 1 1 1 1 1.2750 1.2487 1.2550 1.2613 v 1 0 1 1 1 0 1.2875 1.2612 1.2675 1.2738 v 1 0 1 1 0 1 1.3000 1.2736 1.2800 1.2864 v 1 0 1 1 0 0 1.3125 1.2860 1.2925 1.2990 v 1 0 1 0 1 1 1.3250 1.2985 1.3050 1.3115 v 1 0 1 0 1 0 1.3375 1.3109 1.3175 1.3241 v 1 0 1 0 0 1 1.3500 1.3234 1.3300 1.3367 v 1 0 1 0 0 0 1.3625 1.3358 1.3425 1.3492 v 1 0 0 1 1 1 1.3750 1.3482 1.3550 1.3618 v 1 0 0 1 1 0 1.3875 1.3607 1.3675 1.3743 v 1 0 0 1 0 1 1.4000 1.3731 1.3800 1.3869 v 1 0 0 1 0 0 1.4125 1.3855 1.3925 1.3995 v 1 0 0 0 1 1 1.4250 1.3980 1.4050 1.4120 v 1 0 0 0 1 0 1.4375 1.4104 1.4175 1.4246 v 1 0 0 0 0 1 1.4500 1.4229 1.4300 1.4372 v 1 0 0 0 0 0 1.4625 1.4353 1.4425 1.4497 v 0 1 1 1 1 1 1.4750 1.4477 1.4550 1.4623 v 0 1 1 1 1 0 1.4875 1.4602 1.4675 1.4748 v 0 1 1 1 0 1 1.5000 1.4726 1.4800 1.4874 v 0 1 1 1 0 0 1.5125 1.4850 1.4925 1.5000 v 0 1 1 0 1 1 1.5250 1.4975 1.5050 1.5125 v 0 1 1 0 1 0 1.5375 1.5099 1.5175 1.5251 v 0 1 1 0 0 1 1.5500 1.5224 1.5300 1.5377 v 0 1 1 0 0 0 1.5625 1.5348 1.5425 1.5502 v 0 1 0 1 1 1 1.5750 1.5472 1.5550 1.5628 v 0 1 0 1 1 0 1.5875 1.5597 1.5675 1.5753 v 0 1 0 1 0 1 1.6000 1.5721 1.5800 1.5879 v *vid code is for reference only. ?v out no load is the input to the error amplifier.
ncp5314 http://onsemi.com 6 electrical characteristics (0 c < t a < 70 c; v cc = 12 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 32.4 k , v(i lim ) = 1.0 v, dac code 010100; unless otherwise noted) characteristic test conditions min typ max unit vid inputs input threshold v id5 , v id4 , v id3 , v id2 , v id1 , v id0 400 600 800 mv vid pin current v id5 , v id4 , v id3 , v id2 , v id1 , v id0 = 0 v ? 0.1 1.0 a sgnd bias current sgnd < 300 mv, all dac codes 10 20 40 a sgnd voltage compliance range ? ?200 ? 300 mv power good upper threshold, offset from no load set point 85 100 115 mv lower threshold constant pwrgds/no load set point 0.475 0.500 0.525 v/v output low voltage v ffb = 1.0 v, i pwrgd = 4.0 ma ? 0.15 0.40 v delay v ffb low to pwrgd low 50 232 600 s overvoltage protection ovp threshold above vid ? 170 200 250 mv enable input start threshold gates switching, ss high 0.6 0.7 0.8 v stop threshold gates not switching, ss low 0.4 0.5 0.6 v hysteresis ? ? 200 ? mv input pull?up voltage 1.0 m to gnd 2.7 2.9 3.3 v input pull?up resistance ? 7.0 10 20 k voltage feedback error amplifier v fb bias current ? ? 0.1 1.0 a comp source current comp = 0.5 v to 2.0 v 40 70 100 a comp sink current ? 40 70 100 a transconductance (note 2) 1.1 1.3 1.5 mmho open loop dc gain (note 2) 72 80 ? db unity gain bandwidth c comp = 30 pf (note 2) ? 4.0 ? mhz psrr @ 1.0 khz (note 2) ? 60 ? db comp max voltage v fb = 0 v 2.4 2.7 ? v comp min voltage v fb = 1.6 v ? 50 150 mv pwm comparators minimum pulse width measured from csxp to gatex, v fb = csxn = 0.5, comp = 0.5 v, 60 mv step between csxp and csxn; measure at gatex = 1.0 v ? 40 100 ns transient response time measured from csxn to gatex, comp = 2.1 v, csxp = csxn = 0.5 v, csxn stepped from 1.2 v to 2.0 v ? 40 60 ns channel startup offset csxp = csxn = v fb = 0, measure vcomp when gatex switch high 0.35 0.62 0.75 v artificial ramp amplitude 50% duty cycle ? 100 ? mv mosfet driver enable (drvon) output high drvon floating 2.3 ? ? v output low ? ? ? 0.2 v pull?down resistance drvon = 1.5 v, enable = 0 v, r = 1.5 v/i(drvon) 35 70 140 k source current drvon = 1.5 v 0.5 3.0 6.5 ma 2. guaranteed by design, not tested in production.
ncp5314 http://onsemi.com 7 electrical characteristics (continued) (0 c < t a < 70 c; v cc = 12 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 32.4 k , v(i lim ) = 1.0 v, dac code 010100; unless otherwise noted) characteristic unit max typ min test conditions gates high voltage measure gatex, i gatex = 1.0 ma ? 2.70 ? v low voltage measure gatex, i gatex = 1.0 ma ? 0.5 0.7 v rise time gate 0.8 v < gatex < 2.0 v, v cc = 10 v ? 5.0 10 ns fall time gate 2.0 v > gatex > 0.8 v, v cc = 10 v ? 5.0 10 ns oscillator switching frequency r osc = 32.4 k, 3 phase (note 2) r osc = 32.4 k, 4 phase (note 2) ?15% ?15% 880 660 +15% +15% khz r osc voltage ? 0.95 1.02 1.05 v phase delay, 3 phases v cc = cs4p = cs4n ? 120 ? deg phase delay, 4 phases ? ? 90 ? deg phase disable threshold v cc ? (cs4p = cs4n) 500 ? ? mv adaptive voltage positioning v drp output voltage to dac out offset csxp = csxn, v fb = comp, measure v drp ? comp ?15 ? 15 mv current sense amplifier to v drp gain csxp ? csxn = 80 mv, v fb = comp, measure v drp ? comp 2.25 2.54 2.75 v/v v drp source current ? 1.0 7.0 14 ma v drp sink current ? 0.2 0.4 0.6 ma soft?start charge current ? 30 44 50 a discharge current ? 90 120 150 a comp pull?down current ? 0.2 0.9 2.1 ma current sensing and overcurrent protection csxp input bias current csxn = csxp = 0 v ? 0.1 1.0 a csxn input bias current csxn = csxp = 0 v ? 0.1 1.0 a current sense amp to pwm gain csxn = 0 v, csxp = 80 mv, measure v(comp) when gatex switches high ? 3.1 ? v/v current sense amp to pwm bandwidth (note 2) ? 7.0 ? mhz current sense amp to i lim gain io/(csxp ? csxn), i lim = 0.6 v, gatex not switching 2.85 3.30 3.65 v/v current sense amp to i lim bandwidth (note 2) ? 1.0 ? mhz current limit filter slew rate (note 2) 2.0 5.0 13 mv/ s i lim input bias current i lim = 0 v ? 0.1 1.0 a pulse?by?pulse current limit threshold voltage v(csxp) ? v(csxn) 80 90 110 mv current sense common mode input range (note 2) 0 ? 2.0 v general electrical specifications v cc operating current comp = 0.3 v (no switching) ? 27 35 ma uvlo start threshold ss charging, gatex switching 8.5 9.0 9.5 v uvlo stop threshold gatex not switching, ss & comp discharging 7.5 8.0 8.5 v uvlo hysteresis start ? stop 0.8 1.0 1.2 v 2. guaranteed by design, not tested in production.
ncp5314 http://onsemi.com 8 pin description pin no. pin symbol pin name description 1?3, 30?32 v id0 ?v id5 dac vid inputs vid?compatible logic input used to program the converter output voltage. all high on v id0 ?v id4 generates fault. 8 drvon drive enable logic high enables mosfet drivers, and logic low turns all mosfets off through mosfet drivers. pulled to ground through internal 70 k resistor. 10 v drp output of current sense amplifiers for adaptive voltage positioning the offset above dac voltage is proportional to the sum of inductor current. a resistor from this pin to v fb programs the amount of adaptive voltage positioning. leave this pin open for no adaptive voltage positioning. 23 r osc oscillator frequency adjust resistor to ground programs the oscillator frequency, as shown in oscillator frequency graph figure 7. 24 i lim total current limit resistor divider between r osc and ground programs the average current limit. 29 enable enable a voltage less than the threshold puts the ic in fault mode, discharging ss. connect to system vid pwrgd signal to control powerup sequencing. hysteresis is provided to prevent chatter.
ncp5314 http://onsemi.com 9 figure 2. block diagram phase2 + ? + ? co2 3.1 co2 co2f co2f 10 + ? + ? co3 3.1 co3 co3f co3f 10 + ? + ? co4 3.1 co4 co4f co4f 10 3.3 v ? + ? + 0.7 v 0.5 v enable comparator set dominant s r q pwrgd ss fault latch ? + ? + 3.3 v reference 9.0 v 8.0 v uvlo comparator enable v cc v id5 v id0 v id1 v id2 v id3 v id4 sgnd vid = 11111x dac output + ? reset dominant s r q v cc pwm latch phase4 ? + co4f pwm comparator + co4 ramp4 + ? reset dominant s r q v cc pwm latch phase3 ? + co3f pwm comparator + co3 ramp3 + ? reset dominant s r q v cc pwm latch phase2 ? + co2f pwm comparator + co2 ramp2 + ? reset dominant s r q pwm latch phase1 ? + co1f pwm comparator + co1 ramp1 pulse current comparator pwrls delay ? + v cc set dominant s r q ? + 10 k + ? + ? dac ovp comparator ? + 200 mv ? + 100 mv pwrgd comparator + ? pwrgd comparator + ? 20 mv 0.5 ? + 0.6 v cs1p cs1n cs2p cs2n cs3p cs3n cs4p cs4n co1 3.1 co1 co1f co1f 10 + ? + i lim module oc comparator + ? error amplifier ? + avp buffer v drp + v ffb v fb + ? oscillator phase1 ramp1 ramp2 phase3 ramp3 phase4 ramp4 comp + ? r osc 1.0 v current source generator + ? cs4p ? + v cc ? 0.5 v + ? phase 4 disable comparator gate1 drvon gate2 gate3 gate4 charge current discharge current + ? 900 mv pulse?by?pulse current limit gnd v cc x0.82 x1.06
ncp5314 http://onsemi.com 10 typical performance characteristics figure 3. dac variation versus temperature figure 4. power good delay versus temperature temperature ( c) temperature ( c) 120 100 80 60 40 20 0 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.5 120 100 80 60 40 20 0 220 225 230 235 figure 5. ovp threshold above vid versus temperature figure 6. channel startup offset versus temperature temperature ( c) temperature ( c) 120 100 80 60 40 20 0 200 210 220 230 190 120 100 80 60 40 20 0 400 450 500 550 600 650 700 figure 7. oscillator frequency versus total r osc value figure 8. switching frequency versus temperature (r osc = 32.4 k ) temperature ( c) 120 100 80 60 40 20 0 650 655 660 670 665 675 680 dac variation from nominal (%) 0.2 0.3 0.4 vid = 010100 vid = 111101 vid = 101101 vid = 010101 pwrgd delay ( s) ovp threshold (mv) average channel offset (mv) 4?phase frequency (khz) 4 phase 3 phase 865 870 875 880 885 890 895 3?phase frequency (khz) r osc (ohms) 1000 k 100 k 10 k 100 1000 switching frequency (khz) 3 phase mode 4 phase mode
ncp5314 http://onsemi.com 11 typical performance characteristics figure 9. v rosc versus temperature figure 10. current sense to v drp gain versus temperature temperature ( c) temperature ( c) 120 100 80 60 40 20 0 1.000 1.005 1.010 1.015 1.025 120 100 80 60 40 20 0 2.40 2.45 2.55 2.60 figure 11. soft?start charge current versus temperature figure 12. current sense amplifier to pwm gain versus temperature temperature ( c) temperature ( c) 120 100 80 60 40 20 0 38 39 40 41 44 45 120 100 80 60 40 20 0 2.0 2.2 2.4 2.6 2.8 3.4 3.6 figure 13. cs amp to i lim gain versus temperature figure 14. pulse?by?pulse current limit threshold versus temperature temperature ( c) temperature ( c) 120 100 80 60 40 20 0 3.00 3.05 3.10 3.20 3.25 3.30 3.35 120 100 80 60 40 20 0 80 85 90 100 95 105 110 r osc voltage (v) 1.020 cs to v drp gain (v/v) ss charge current ( a) current sense amp gain (v/v) current sense to i lim gain (v/v) ip lim threshold voltage (mv) 2.50 42 43 3.0 3.2 3.15
ncp5314 http://onsemi.com 12 typical performance characteristics figure 15. v cc operating current versus temperature temperature ( c) 120 100 80 60 40 20 0 22 23 24 25 30 i cc current (ma) 29 26 27 28 figure 16. operating waveforms v cc enable v ref fault uvlo fault fault reset fault latch fault drvon ss comp v out i out pwrgd power?on enabled startup normal operation pulse?by?pulse current limit overcurrent latchoff power?off to reset oc fault power?on enabled startup uvlo power?off to reset oc fault power?on enabled startup overvoltage power?off
ncp5314 http://onsemi.com 13 theory of operation overview the ncp5314 dc/dc controller from on semiconductor was developed using the enhanced v 2 topology. enhanced v 2 combines the original v 2 topology with peak current?mode control for fast transient response and current sensing capability. the addition of an internal pwm ramp and implementation of fast?feedback directly from vcore has improved transient response and simplified design. this controller can be adjusted to operate as a two?, three? or four?phase controller. differential current sensing provides improved current sharing and easier layout. the ncp5314 includes power good (pwrgd), providing a highly integrated solution to simplify design, minimize circuit board area, and reduce overall system cost. two advantages of a multi?phase converter over a single?phase converter are current sharing and increased effective output frequency. current sharing allows the designer to use less inductance in each phase than would be required in a single?phase converter. the smaller inductor will produce larger ripple currents but the total per?phase power dissipation is reduced because the rms current is lower. transient response is improved because the control loop will measure and adjust the current faster with a smaller output inductor. increased effective output frequency is desirable because the off?time and the ripple voltage of the multi?phase converter will be less than that of a single?phase converter. fixed frequency multi?phase control in a multi?phase converter, multiple converters are connected in parallel and are switched on at different times. this reduces output current from the individual converters and increases the ripple frequency. because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. the ncp5314 controller uses four?phase, fixed?frequency, enhanced v 2 architecture to measure and control currents in individual phases. in four phase mode, each phase is delayed 90 from the previous phase (120 in three?phase mode). normally, gatex transitions to a high voltage at the beginning of each oscillator cycle. inductor current ramps up until the combination of the amplified current sense signal, the internal ramp and the output voltage ripple trip the pwm comparator and bring gatex low. once gatex goes low, it will remain low until the beginning of the next oscillator cycle. while gatex is high, the enhanced v 2 loop will respond to line and load variations. on the other hand, once gatex is low, the loop cannot respond until the beginning of the next pwm cycle. therefore, constant frequency enhanced v 2 will typically respond to disturbances within the off?time of the converter. figure 17. enhanced v 2 control employing resistive current sensing and internal ramp + ? swnode lx rlx rsx csxp csa cox csxn + v out (v core ) ?fast?feedback? connection + ? pwm comp to f/f reset channel startup offset ? + e.a. dac out v fb comp internal ramp + x = 1, 2, 3 or 4 v ffb + ? the enhanced v 2 architecture measures and adjusts the output current in each phase. an additional dif ferential input (csxn and csxp) for inductor current information has been added to the v 2 loop for each phase as shown in figure 17. the triangular inductor current is measured differentially across rs, amplified by csa and summed with the channel startup of fset, the internal ramp and the output voltage at the non?inverting input of the pwm comparator. the purpose of the internal ramp is to compensate for propagation delays in the ncp5314. this provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation and pwm duty cycles above 50% without external slope compensation. as the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the pwm comparator rises and terminates the pwm cycle. if the inductor starts a cycle with higher current, the pwm cycle will terminate earlier providing negative feedback. the ncp5314 provides a differential current sense input (csxn and csxp) for each phase. current sharing is accomplished by referencing all phases to the same comp pin, so that a phase with a larger
ncp5314 http://onsemi.com 14 current signal will turn off earlier than a phase with a smaller current signal. enhanced v 2 responds to disturbances in v core by employing both ?slow? and ?fast? voltage regulation. the internal error amplifier performs the slow regulation. depending on the gain and frequency compensation set by the amplifier?s external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in one or two pwm cycles. fast voltage feedback is implemented by a direct connection from vcore to the non?inverting pin of the pwm comparator via the summation with the inductor current, internal ramp and offset. a rapid increase in output current will produce a negative offset at vcore and at the output of the summer. this will cause the pwm duty cycle to increase almost instantly. fast feedback will typically adjust the pwm duty cycle in one pwm cycle. as shown in figure 17, an internal ramp (nominally 100 mv at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the pwm comparator. this additional ramp compensates for propagation time delays from the current sense amplifier (csa), the pwm comparator and the mosfet gate drivers. as a result, the minimum on time of the controller is reduced and lower duty?cycles may be achieved at higher frequencies. also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the r csx c csx time constant of the feedback components from v core to the csx pin. including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. when the average output current is zero, the comp pin will be: v comp v out @0a channel_startup_offset int_ramp g csa ext_ramp 2 int_ramp is the ?partial? internal ramp value at the corresponding duty cycle, ext_ramp is the peak?to?peak external steady?state ramp at 0 a, g csa is the current sense amplifier gain (nominally 3.0 v/v) and the channel startup offset is typically 0.60 v. the magnitude of the ext_ramp can be calculated from: ext_ramp d (v in v out ) (r csx c csx f sw ) for example, if v out at 0 a is set to 1.480 v with avp and the input voltage is 12.0 v, the duty cycle (d) will be 1.48/12.0 or 12.3%. int_ramp will be 100 mv/50% ? 12.3% = 25 mv. realistic values for r csx , c csx and f sw are 10 k , 0.015 f and 650 khz. using these and the previously mentioned formula, ext_ramp will be 15.0 mv. v comp 1.48 v 0.62 v 25 mv 2.65 v v 15.0 mv 2 2.145 vdc swnode v fb (v out ) internal ramp csa out w/ exaggerated delays comp?offset csa out + ramp + cs ref t1 t2 figure 18. open loop operation if the comp pin is held steady and the inductor current changes, there must also be a change in the output voltage or, in a closed loop configuration when the output current changes, the comp pin must move to keep the same output voltage. the required change in the output voltage or comp pin depends on the scaling of the current feedback signal and is calculated as: v r s g csa i out the single?phase power stage output impedance is: s ingle stage impedance v out i out r s g csa the total output impedance will be the single stage impedance divided by the number of phases in operation. the output impedance of the power stage determines how the converter will respond during the first few microseconds of a transient before the feedback loop has repositioned the comp pin. the peak output current can be calculated from: i out,peak (v comp v out offset) (r s g csa ) figure 18 shows the step response of the comp pin at a fixed level. before t1, the converter is in normal steady?state operation. the inductor current provides a portion of the pwm ramp through the current sense amplifier. the pwm cycle ends when the sum of the current ramp, the ?partial? internal ramp voltage signal and offset exceed the level of the comp pin. at t1, the output current increases and the output voltage sags. the next pwm cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the v fb pin and the cycle ends at t2. after t2, the output voltage remains lower than at light load and the average current signal level (csx output) is raised so that the sum of the current and voltage signal is the same as with the original load. in a closed
ncp5314 http://onsemi.com 15 loop system, the comp pin would move higher to restore the output voltage to the original level. inductive current sensing for lossless sensing, current can be measured across the inductor as shown in figure 19. in the diagram, l is the output inductance and r l is the inherent inductor resistance. to compensate the current sense signal, the values of r csx and c csx are chosen so that l/r l = r csx ? c csx . if this criteria is met, the current sense signal should be the same shape as the inductor current and the voltage signal at csx will represent the instantaneous value of inductor current. also, the circuit can be analyzed as if a sense resistor of value r l was used. figure 19. enhanced v 2 control employing lossless inductive current sensing and internal ramp + ? swnode lx r csx rlx csxp csa cox csxn + v out (v core ) ?fast?feedback? connection + ? pwm comp to f/f reset channel startup offset ? + e.a. dac out v fb comp internal ramp + x = 1, 2, 3 or 4 c csx + ? v ffb when choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. copper magnet wire has a temperature coefficient of 0.39% per c. the increase in winding resistance at higher temperatures should be considered when setting the ocset threshold. if a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in figure 17. current sharing accuracy printed circuit board (pcb) traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. for accurate current sharing, the current sense inputs should sense the current at relatively the same points for each phase. in some cases, especially with inductive sensing, resistance of the pcb can be useful for increasing the current sense resistance. the total current sense resistance used for calculations must include any pcb trace resistance that carries inductor current between the csxp input and the csxn input. current sense amplifier (csa) input mismatch and the value of the current sense component will determine the accuracy of the current sharing between phases. the worst case csa input mismatch is 10 mv and will typically be within 4.0 mv. the difference in peak currents between phases will be the csa input mismatch divided by the current sense resistance. if all current sense components are of equal resistance, a 3.0 mv mismatch with a 2.0 m sense resistance will produce a 1.5 a dif ference in current between phases. external ramp size and current sensing the internal ramp allows flexibility in setting the current sense time constant. t ypically, the current sense r csx ? c csx time constant should be equal to or slightly slower than the inductor?s time constant. if rc is chosen to be smaller (faster) than l/r l , the ac or transient portion of the current sensing s ignal will be scaled larger than the dc portion. this will provide a larger steady?state ramp, but circuit performance will be affected and must be evaluated carefully. the current signal will overshoot during transients and settle at the rate determined by r csx ? c csx . it will eventually settle to the correct dc level, but the error will decay with the time constant of r csx ? c csx . if this error is excessive, it will affect transient response, adaptive positioning and current limit. during a positive current transient, the comp pin will be required to undershoot in response to the current signal in order to maintain the output voltage. similarly, the v drp signal will overshoot which will produce too much transient droop in the output voltage. the single?phase pulse?by?pulse overcurrent protection will trip earlier than it would if compensated correctly and hiccup?mode current limit will have a lower threshold for fast rising step loads than for slowly rising output currents.
ncp5314 http://onsemi.com 16 figure 20. inductive sensing waveform during a load step with fast rc time constant (50 s/div) the waveforms in figure 20 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of l = 500 nh, r l = 1.6 m , r csx = 20 k and c csx = .01 f. in this case, ideal current signal compensation would require r csx to be 31 k . due to the faster than ideal rc time constant, there is an overshoot of 50% and the overshoot decays with a 200 s time constant. with this compensation, the i lim pin threshold must be set more than 50% above the full load current to avoid triggering current limit during a large output load step. transient response and adaptive voltage positioning for applications with fast transient currents, the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. adaptive voltage positioning can reduce peak?peak output voltage deviations during load transients and allow for a smaller output filter. the output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is applied. similarly, the output voltage can be set lower than nominal during heavy loads to reduce overshoot when the load current is removed. for low current applications, a droop resistor can provide fast, accurate adaptive positioning. however, at high currents, the loss in a droop resistor becomes excessive. for example, a 50 a converter with a 1 m resistor would provide a 50 mv change in output voltage between no load and full load and would dissipate 2.5 w. lossless adaptive voltage positioning (avp) is an alternative to using a droop resistor, but it must respond to changes in load current. figure 21 shows how avp works. the waveform labeled ?normal? shows a converter without avp. on the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. with fast (ideal) avp, the peak?to?peak excursions are cut in half. in the slow avp waveform, the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. the controller can be configured to adjust the output voltage based on the output current of the converter. (refer to the application diagram in figure 1). the no?load positioning is now set internally to vid ? 20 mv, reducing the potential error due to resistor and bias current mismatches. in order to realize the avp function, a resistor divider network is connected between v fb , v drp and v out . during no?load conditions, the v drp pin is at the same voltage as the v fb pin. as the output current increases, the v drp pin voltage increases proportionally. this drives the v fb voltage higher, causing v out to ?droop? according to a loadline set by the resistor divider network. the response during the first few microseconds of a load transient is controlled primarily by power stage output impedance, and by the esr and esl of the output filter. the transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. if the ramp size is too large or the error amp too slow, there will be a long transition to the final voltage after a transient. this will be most apparent with low capacitance output filters. adaptive positioning adaptive positioning normal fast slow limits figure 21. adaptive voltage positioning overvoltage protection overvoltage protection (ovp) is provided as a result of the normal operation of the enhanced v 2 control topology with synchronous rectifiers. the control loop responds to an overvoltage condition within 40 ns, causing the gatex output to shut off. the (external) mosfet driver should react normally to turn off the top mosfet and turn on the bottom mosfet. this results in a ?crowbar? action to clamp the output voltage and prevent damage to the load. the regulator will remain in this state until the fault latch is reset by cycling power at the v cc pin. power good according to the latest specifications, the power good (pwrgd) signal must be asserted when the output voltage is within a window defined by the vid code, as shown in figure 22. the pwrls pin is provided to allow the pwrgd comparators to accurately sense the output voltage. the effect of the pwrgd lower threshold can be modified using a resistor divider from the output to pwrls to ground, as shown in figure 23.
ncp5314 http://onsemi.com 17 since the internally?set thresholds for pwrls are vid/2 for the lower threshold and vid + 80 mv for the upper threshold, a simple equation can be provided to assist the designer in selecting a resistor divider to provide the desired pwrgd performance. v lower v vid 2 r 1 r 2 r 1 v upper v vid 80 mv the logic circuitry inside the chip sets pwrgd low only after a delay period has been passed. a ?power bad? event does not cause pwrgd to go low unless it is sustained through the delay time of 250 s. if the anomaly disappears before the end of the delay, the pwrgd output will never be set low. in order to use the pwrgd pin as specified, the user is advised to connect external resistors as necessary to limit the current into this pin to 4 ma or less. pwrgd ??? ??? ??? ??? ??? ??? v lower vid + 80 mv v out high low p wrgd ?2.6% +2.6 % ?5.0% +5.0 % figure 22. pwrgd assertion window low pwrgd lo- w pwrgd high figure 23. adjusting the pwrgd threshold v out r1 r2 pwrls undervoltage lockout the ncp5314 includes an undervoltage lockout circuit. this circuit keeps the ic?s output drivers low until v cc applied to the ic reaches 9 v. the gate outputs are disabled when v cc drops below 8 v. soft?start at initial power?up, both ss and comp voltages are zero. the total ss capacitance will begin to charge with a current of 40 a. the error amplifier directly charges the comp capacitance. an internal clamp ensures that the comp pin voltage will always be less than the voltage at the ss pin, ensuring proper startup behavior. all gate outputs are held low until the comp voltage reaches 0.6 v. once this threshold is reached, the gate outputs are released to operate normally. current limit two levels of over?current protection are provided. first, if the voltage between the current sense pins (csxn and csxp) exceeds the fixed threshold (single pulse current limit), the pwm comparator is turned off. this provides fast peak current protection for individual phases. second, the individual phase currents are summed and externally low?pass filtered to compare an averaged current signal to a user adjustable voltage on the i lim pin. if the i lim voltage is exceeded, the fault latch trips and the converter is latched off. v cc must be recycled to reset the latch. fault protection logic the ncp5314 includes fault protection circuitry to prevent harmful modes of operation from occurring. the fault logic is described in table 1. gate outputs the ncp5314 is designed to operate with external gate drivers. accordingly, the gate outputs are capable of driving a 100 pf load with typical rise and fall times of 5 ns. digital to analog converter (dac) the output voltage of the ncp5314 is set by means of a 6?bit, 0.5% dac. the vid pins must be pulled high externally. a 1.5 k pullup to a maximum of 3.3 v is recommended to meet intel specifications. to ensure valid logic signals, the designer should ensure at least 800 mv will be present at the ic for a logic high. the output of the dac is described in the electrical characteristics section of the data sheet. these outputs are consistent with vr10.x and processor specifications. the dac output is 20 mv below the vid code specification. the latest vrm and processor specifications require a power supply to turn its output off in the event of a 1 1111x vid code. when the dac sees such a code, the gate pins stop switching and go low. this condition is described in table 1. adjusting the number of phases the ncp5314 was designed with a selectable?phase architecture. designers may choose any number of phases up to four. the phase delay is automatically adjusted to match the number of phases that will be used. this feature allows the designer to select the number of phases required for a particular application. four?phase operation is standard. all phases switch with a 90 degree delay between pulses. no special connections are required. three?phase operation is achieved by disabling phase 4. tie together cs4n and cs4p, and then pull both pins to v cc . the remaining phases will continue to switch, but now there
ncp5314 http://onsemi.com 18 will be a 120 degree delay between pulses. the phase firing order w ill become 1?2?3. two? and single?phase operation may be realized as well. first, the designer must choose the proper phases. two phase operation must use phase 2 and 4 by tying cs1n, cs1p, cs3n and cs3p to ground. this will then use phase 2 and 4 as the gate drivers. the other gate drives may switch, so leave them unconnected. single phase is best accomplished by using only phase 2 as the switch controller. conn ect cs2p and cs2n pins to the current sense capacitor and the gate drive to the driver ic. tie all other csxx pins together and connect them to ground. table 1. description of fault logic faults results stop switching pwrgd level driver enable ss characteristics reset method overvoltage lockout yes low high ?0.3 ma power on enable low yes depends on output voltage level low ?0.3 ma not affected module overcurrent limit yes depends on output voltage level low ?0.3 ma power on dac code = 1 1111x yes depends on output voltage level low ?0.3 ma valid vid v ref undervoltage lockout yes depends on output voltage level low ?0.3 ma power on pwrls out of range no low high not affected not affected applications information 1. setting converter operating frequency the total resistance from r osc to ground sets the operating frequency for each phase of the converter. the frequency can be set for either the three phase or four phase mode by using figure 7, ?oscillator frequency versus t otal r osc value.? after choosing the desired operating frequency and the number of phases, use the figure to determine the necessary resistance. if two phase operation is desired, use the value given for four phase operation. the voltage from r osc is closely regulated at 1 v. this voltage can be used as the reference for the overcurrent limit set point on the i lim pin. design a voltage divider with the appropriate division ratio to give the desired i lim voltage and total resistance to set the operating frequency. since loading by the i lim pin is very small, the frequency selection will not be affected. 2. output capacitor selection the output capacitors filter the current from the output inductor and provide a low impedance for transient load current changes. typically, microprocessor applications require both bulk (electrolytic, tantalum) and low impedance, high frequency (ceramic) types of capacitors. the bulk capacitors provide ?hold up? during transient loading. the low impedance capacitors reduce steady?state ripple and bypass the bulk capacitance when the output current changes very quickly. the microprocessor manufacturers usually specify a minimum number of ceramic capacitors. the designer must determine the number of bulk capacitors. choose the number of bulk output capacitors to meet the peak transient requirements. the formula below can be used to provide a starting point for the minimum number of bulk capacitors (n out,min ): n out,min esr per capacitor i o,max v o,max (1) in reality, both the esr and esl of the bulk capacitors determine the voltage change during a load transient according to: v o,max ( i o,max t) esl i o,max esr (2 ) unfortunately, capacitor manufacturers do not specify the esl of their components and the inductance added by the pcb traces is highly dependent on the layout and routing. therefore, it is nec essary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors. the latest intel processor specifications discuss ?dynamic vid? (dvid), in which the vid codes are stepped up or down to a new desired output voltage. due to the timing requirements at which the output must be in regulation, the output capacitor selection becomes more complicated. the ideal output capacitor selection has low esr and low capacitance. too much output capacitance will make it difficult to meet dvid timing specifications; too much esr will complicate the transient solution. the sanyo 4sp560m and panasonic eeu?fl provide a good balance of capacitance vs. esr.
ncp5314 http://onsemi.com 19 3. output inductor selection the output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady?state and transient performance of the converter. when selecting an inductor, the designer must consider factors such as dc current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size and cost (usually the primary concern). in general, the output inductance value should be electrically and physically as small as possible to provide the best transient response at minimum cost. if a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. on the other hand, too low an inductance value will result in very large ripple currents in the power components (mosfets, capacitors, etc.) resulting in increased dissipation and lower converter efficiency. increased ripple currents force the designer to use higher rated mosfet s, oversize the thermal solution, and use more, higher rated input and output capacitors, adversely affecting converter cost. one method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. lower ripple currents will result in less core and mosfet losses and higher converter efficiency. equation 3 may be used to calculate the minimum inductor value to produce a given maximum ripple current ( ) per phase. the inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. conversely, higher inductor values will result in less than the selected maximum ripple current. lo min (v in v out ) v out ( i o,max v in f sw ) (3) is the ripple current as a percentage of the maximum output current per phase ( = 0.15 for 15%, = 0.25 for 25%, etc.). if the minimum inductor value is used, the inductor current will swing % about its value at the center. therefore, for a four?phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + ) ? i o,max /4. the maximum inductor value is limited by the transient response of the converter. if the converter is to have a fast transient response, the inductor should be made as small as possible. if the inductor is too large its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required and the converter cost will be increased. for a given inductor value, it is useful to determine the times required to increase or decrease the current. for increasing current: t inc lo i o (v in v out ) (3.1) for decreasing current: t dec lo i o (v out ) (3.2) for typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. thus, it may be more dif ficult for the converter to stay within the regulation limits when the load is removed than when it is applied and excessive overshoot may result. the output voltage ripple can be calculated using the output inductor value derived in this section (lo min ), the number of output capacitors (n out,min ) and the per capacitor esr determined in the previous section: v out,p?p (esr per cap n out,min ) (v in #phases v out ) d (lo min f sw ) (4 ) this formula assumes steady?state conditions with no more than one phase on at any time. the second term in equation 4 is the total ripple current seen by the output capacitors. the total output ripple current is the ?time summation? of the four individual phase currents that are 90 degrees out?of?phase. as the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. therefore, the total output ripple current and voltage are reduced in a multi?phase converter. 4. input capacitor selection the choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. the designer must choose capacitors that will support the worst case input voltage with adequate margin. to calculate the number of input capacitors, one must first determine the total rms input ripple current. to this end, begin by calculating the average input current to the converter: i in,avg i o,max d (5) where: d is the duty cycle of the converter, d = v out /v in ; is the specified minimum efficiency; i o,max is the maximum converter output current. the input capacitors will discharge when the control fet is on and charge when the control fet is off as shown in figure 24. the following equations will determine the maximum and minimum currents delivered by the input capacitors: i c,max i lo,max i in,avg (6) i c,min i lo,min i in,avg (7) i lo,max is the maximum output inductor current: i lo,max i o,max i lo 2 (8) where is the number of phases in operation. i lo,min is the minimum output inductor current: i lo,min i o,max i lo 2 (9)
ncp5314 http://onsemi.com 20 i c,max i c,min 0 a ?i in,avg fet on, caps discharging fet off, caps charging t on t/4 i c,in = i c,max ? i c,min figure 24. input capacitor current for a four?phase converter i lo is the peak?to?peak ripple current in the output inductor of value lo: i lo (v in v out ) d (lo f sw ) (10) for the four?phase converter, the input capacitor(s) rms current is then: i cin,rms [4d (i c,min 2 i c,min i c,in i c,in 2 3) i in,avg 2 (1 4d)] 1 2 (11) select the number of input capacitors (n in ) to provide the rms input current (i cin,rms ) based on the rms ripple current rating per capacitor (i rms,rated ): n in i cin,rms i rms,rated (12) for a four?phase converter with perfect efficiency ( = 1), the worst case input ripple?current will occur when the converter is operating at a 12.5% duty cycle. at this operating point, the parallel combination of input capacitors must support an rms ripple current equal to 12.5% of the converter?s dc output current. at other duty cycles, the ripple?current will be less. for example, at a duty cycle of either 6% or 19%, the four?phase input ripple?current will be approximately 10% of the converter?s dc output current. in general, capacitor manufacturers require derating to the specified ripple?current based on the ambient temperature. more capacitors will be required because of the current derating. the designer should know the esr of the input capacitors. the input capacitor power loss can be calculated from: p cin i cin,rms 2 esr_per_capacitor n in (13) low esr capacitors are recommended to minimize losses and reduce capacitor heating. the life of an electrolytic capacitor is reduced 50% for every 10 c rise in the capacitor?s temperature. 5. input inductor selection the use of an inductor between the input capacitors and the power source will accomplish two objectives. first, it will isolate the voltage source and the system from the noise generated in the switching supply. second, it will limit the inrush current into the input capacitors at power up. large inrush currents reduce the expected life of the input capacitors. the inductor?s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. the worst case input current slew rate will occur during the first few pwm cycles immediately after a step?load change is applied as shown in figure 25. when the load is applied, the output voltage is pulled down very quickly. current through the output inductors will not change instantaneously, so the initial transient load current must be conducted by the output capacitors. the output voltage will step downward depending on the magnitude of the output current (i o,max ), the per capacitor esr of the output capacitors (esr out ) and the number of the output capacitors (n out ) as shown in figure 25. assuming the load current is shared equally between all phases, the output voltage at full transient load will be: v out,full?load (14) v out,no?load (i o,max ) esr out n out when the control mosfet (q1 in figure 25) turns on, the input voltage will be applied to the opposite terminal of the output inductor (the swnode). at that instant, the voltage across the output inductor can be calculated as: v lo v in v out,full?load (15) v in v out,no?load (i o,max ) esr out n out the differential voltage across the output inductor will cause its current to increase linearly with time. the slew rate of this current can be calculated from: di lo dt v lo lo (16) current changes slowly in the input inductor so the input capacitors must initially deliver the vast majority of the input current. the amount of voltage drop across the input capacitors ( v ci ) is determined by the number of input capacitors (n in ), their per capacitor esr (esr in ) and the current in the output inductor according to: v ci esr in n in di lo dt t on esr in n in di lo dt d f sw (17) before the load is applied, the voltage across the input inductor (v li ) is very small and the input capacitors charge to the input voltage v in . after the load is applied, the voltage drop across the input capacitors, v ci , appears across the input i nductor as well. knowing this, the minimum value of the input inductor can be calculated from: li min v li di in dt max v ci di in dt max (18) di in /dt max is the maximum allowable input current slew rate.
ncp5314 http://onsemi.com 21 the input inductance value calculated from equation 18 is relatively conservative. it assumes the supply voltage is very ?stiff? and does not account for any parasitic elements that will limit di/dt such as stray inductance. also, the esr values of the capacitors specified by the manufacturer?s data sheets are worst case high limits. in reality, input voltage ?sag,? lower capacitor esrs and stray inductance will help reduce the slew rate of the input current. as with the output inductor, the input inductor must support the maximum current without saturating the inductor. also, for an inexpensive iron powder core, such as the ?26 or ?52 from micrometals, the inductance ?swing? with dc bias must be taken into account and inductance will decrease as the dc input current increases. at the maximum input current, the inductance must not decrease below the minimum value or the di/dt will be higher than expected. 6. mosfet and heatsink selection power dissipation, package size and thermal requirements drive mosfet selection. to adequately size the heat sink, the design must first predict the mosfet power dissipation. once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the control or upper mosfet will display both switching and conduction losses. the synchronous or lower mosfet will exhibit only conduction losses because it switches into nearly zero voltage. however, the body diode in the synchronous mosfet will suffer diode losses during the non?overlap time of the gate drivers. + + vi 12 v li tbd n ci ci esr ci /n ci q2 q1 lo esr co /n co 14 u(t) n co co vi(t = 0) = 12 v swnode vo(t = 0) = 1.745 v v ci i lo v out i li max di/dt occurs in first few pwm cycles. figure 25. calculating the input inductance + ? i d v gate v drain q gd q gs2 q gs1 v gs_th figure 26. mosfet switching characteristics for the upper or control mosfet, the power dissipation can be approximated from: p d,control (i rms,cntl 2 r ds(on) ) (i lo,max q switch i g v in f sw ) (q oss 2 v in f sw ) (v in q rr f sw ) (19) the first term represents the conduction or ir losses when the mosfet is on while the second term represents the switching losses. the third term is the loss associated with the control and synchronous mosfet output charge when the control mosfet turns on. the output losses are caused by both the control and synchronous mosfet but are dissipated only in the control fet. the fourth term is the loss due to the reverse recovery time of the body diode in the synchronous mosfet. the first two terms are usually adequate to predict the majority of the losses.
ncp5314 http://onsemi.com 22 i rms,cntl is the rms value of the trapezoidal current in the control mosfet: (20) i rms,cntl d [(i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 i lo,max is the maximum output inductor current: i lo,max i o,max i lo 2 (21) i lo,min is the minimum output inductor current: i lo,min i o,max i lo 2 (22) i o,max is the maximum converter output current. d is the duty cycle of the converter: d v out v in (23) i lo is the peak?to?peak ripple current in the output inductor of value l o : i lo (v in v out ) d (lo f sw ) (24) r ds(on) is the on resistance of the mosfet at the applied gate drive voltage. q switch is the post gate threshold portion of the gate?to?source charge plus the gate?to?drain charge. this may be specified in the data sheet or approximated from the gate?charge curve as shown in the figure 26. q switch q gs2 q gd (25) i g is the output current from the gate driver ic. v in is the input voltage to the converter. f sw is the switching frequency of the converter. q g is the mosfet total gate charge to obtain r ds(on) ; commonly specified in the data sheet. v g is the gate drive voltage. q rr is the reverse recovery charge of the lower mosfet. q oss is the mosfet output charge specified in the data sheet. for the lower or synchronous mosfet, the power dissipation can be approximated from: p d,synch (i rms,synch 2 r ds(on) ) (vf diode i o,max 2 t_nonoverlap f sw ) (26) where: vf diode is the forward voltage of the mosfet?s intrinsic diode at the converter output current. t_nonoverlap is the non?overlap time between the upper and lower gate drivers to prevent cross conduction. this time is usually specified in the data sheet for the control ic. the first term represents the conduction or ir losses when the mosfet is on and the second term represents the diode losses that occur during the gate non?overlap time. all terms were defined in the previous discussion for the control mosfet with the exception of: (27) i rms,synch 1 d [(i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 when the mosfet power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature. t
(t j t a ) p d (28) where: t is the total thermal impedance ( jc + sa ); jc is the junction?to?case thermal impedance of the mosfet; sa is the sink?to?ambient thermal impedance of the heatsink assuming direct mounting of the mosfet (no thermal ?pad? is used); t j is the specified maximum allowed junction temperature; t a is the worst case ambient operating temperature. for to?220 and to?263 packages, standard fr?4 copper clad circuit boards will have approximate thermal resistances ( sa ) as shown below: pad size (in 2 /mm 2 ) single?sided 1 oz copper 0.50/323 60?65 c/w 0.75/484 55?60 c/w 1.00/645 50?55 c/w 1.50/968 45?50 c/w as with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading and component variations (i.e., worst case mosfet r ds(on) ). also, the inductors and capacitors share the mosfet?s heatsinks and will add heat and raise the temperature of the circuit board and mosfet. for any new design, it is advisable to have as much heatsink area as possible. all too often, new designs are found to be too hot and require re?design to add heatsinking. 7. adaptive voltage positioning two resistors program the adaptive voltage positioning (avp): r fb and r drp . these components form a resistor divider, shown in figures 27 and 28, between v drp , v fb , and v out . resistor r fb is connected between v out and the v fb pin of the controller. at no load, this resistor will conduct the very small internal bias current of the v fb pin. therefore v fb should be kept below 10 k to avoid output voltage error due to the input bias current. if the r fb resistor is kept small, the v fb bias current can be ignored. resistor r drp is connected between the v drp and v fb pins of the controller. at no load, these pins should be at an equal potential, and no current should flow through r drp . in reality, the bias current coming out of the v drp pin is likely to have a small positive voltage with respect to v fb . this current produces a small decrease in output voltage at no load, which can be minimized by keeping the r drp resistor
ncp5314 http://onsemi.com 23 below 30 k . as load current increases, the voltage at the v drp pin rises. the ratio of the r drp and r fb resistors causes the voltage at the v fb pin to rise, reducing the output voltage. figure 29 shows the dc effect of avp, given an appropriate resistor ratio. to choose components, recall that the two resistors r fb and r drp form a voltage divider. select the appropriate resistor ratio to achieve the desired loadline. at no load, the output voltage is positioned 20 mv below the dac output setting. the output voltage droop will follow the equation: r drp g r l r fb r ll (29) where: g = current sense amplifier to v drp gain (v/v); r l = esr of lo inductor (m ); r ll = load line resistance (m ). ? + + ? r cs1 cs1p c cs1 l1 0 a g vdrp + ? r csx csxp c csx lx 0 a g vdrp comp error amp vid ? 20 mv r drp r fb v drp = vid v fb = vid ? 20 mv v core i drp = 0 i fb = 0 v core = vid + ibias vfb r fb figure 27. avp circuitry at no?load + ? cs1n csxn ? + + ? r cs1 cs1p c cs1 l1 i max /2 g vdrp + ? r csx csxp c csx lx i max /n g vdrp comp error amp vid ? 20 mv r drp r fb v drp = vid + i max ? r l ? g vdrp v fb = vid ? 20 mv v core i drp i fb v core = vid ? i drp r fb figure 28. avp circuitry at full?load i drp = i max ? r l ? g vdrp /r drp i fbk = i drp = vid ? i max r l g vdrp r fb /r drp + ? cs1n csxn
ncp5314 http://onsemi.com 24 ?0.14 ?0.06 ?0.02 0 v out (v) 0 i out (a) 10 6 0 ?0.04 ?0.08 ?0.10 ?0.12 20 30 40 50 vid ? v out spec min spec max figure 29. the dc effects of avp vs. load it is easiest to select a value for r fb and then evaluate the equation to find r drp . r ll is simply the desired output voltage droop divided by the output current. if inductor sensing is used, r l will be the resistance of the inductor, assuming that the current sense network equation (eq. 30) is valid. refer to the discussion on current sensing for further information. 8. current sensing current sensing is used to balance current between different phases, to limit the maximum phase current and to limit the maximum system current. since the current information, sensed across the inductor, is a part of the control loop, better stability is achieved if the current information is accurate and noise?free. the ncp5314 introduces a novel feature to achieve the best possible performance: differential current sense amplifiers. two sense lines are routed for each phase, as shown in figure 28. for inductive current sensing, choose the current sense network (r csx , c csx , x = 1, 2, 3 or 4) to satisfy r csx c csx lo (r l r pcb ) (30) this will provide an adequate starting point for r csx and c csx . after the converter is constructed, the value of r csx (and/or c csx ) should be fine?tuned in the lab by observing the v drp signal during a step change in load current. tune the r csx ? c csx network by varying r csx to provide a ?square?wave? at the v drp output pin with maximum rise time and minimal overshoot as shown in figure 32. figure 30. v drp tuning waveforms. the rc time constant of the current sense network is too long (slow): v drp and v out respond too slowly. figure 31. v drp tuning waveforms. the rc time constant of the current sense network is too short (fast): v drp and v out both overshoot. figure 32. v drp tuning waveforms. the rc time constant of the current sense network is optimal: v drp and v out respond to the load current quickl y without overshooting.
ncp5314 http://onsemi.com 25 9. error amplifier tuning after the steady?state (static) avp has been set and the current sense network has been optimized, the error amplifier must be tuned. the gain of the error amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the error amplifier?s feedback capacitor (c amp in the applications diagram). the bandwidth of the control loop will vary directly with the gain of the error amplifier. if c amp is too large, the loop gain/bandwidth will be low, the comp pin will slew too slowly and the output voltage will overshoot as shown in figure 33. on the other hand, if c amp is too small, the loop gain/bandwidth will be high, the comp pin will slew very quickly and overshoot will occur. integrator ?wind up? is the cause of the overshoot. in this case, the output voltage will transition more slowly because comp spikes upward as shown in figure 34. too much loop gain/bandwidth increases the risk of instability. in general, one should use the lowest loop gain/bandwidth possible to achieve acceptable transient response. this will insure good stability. if c amp is optimal, the comp pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in figure 35. after the control loop is tuned to provide an acceptable transient response, the steady?state voltage ripple on the comp pin should be examined. when the converter is operating at full steady?state load, the peak?to?peak voltage ripple (v pp ) on the comp pin should be less than 20 mv pp as shown in figure 36. less than 10 mv pp is ideal. excessive ripple on the comp pin will contribute to jitter. figure 33. the value of c amp is too high and the loop gain/bandwidth too low. comp slews too slowly which results in overshoot in v out . figure 34. the value of c amp is too low and the loop gain/bandwidth too high. comp moves too quickly, which is evident from the small spike in its voltage when the load is applied or removed. the output voltage transitions more slowly because of the comp spike. figure 35. the value of c amp is optimal. comp slews quickly without spiking or ringing. v out does not overshoot and monotonically settles to its final value. figure 36. at full?load the p eak?to?peak voltage ripple on the comp pin should be less than 20 mv for a well?tuned/stable controller. higher comp voltage ripple will contribute to output voltage jitter .
ncp5314 http://onsemi.com 26 10. current limit setting when the output of the current sense amplifier (cox in the block diagram) exceeds the voltage on the i lim pin, the part will latch off. for inductive sensing, the i lim pin voltage should be set based on the inductor?s maximum resistance (r lmax ). the design must consider the inductor?s resistance increase due to current heating and ambient temperature rise. also, depending on the current sense points, the circuit board may add additional resistance. in general, the temperature coef ficient of copper is +0.39% per c. to set the level of the i lim pin: v ilim (i out,lim i lo 2) r g ilim (31) where: i out,lim is the current limit threshold of the converter; i lo /2 is half the inductor ripple current; r is r lmax + r pcb; g ilim is the current sense to i lim gain. for the overcurrent protection to work properly, the current sense time constant (rc) should be slightly larger than the r l time constant. if the rc time constant is too fast, a step load change will cause the sensed current waveform to appear larger than the actual inductor current and will trip the current limit at a lower level than expected.
ncp5314 http://onsemi.com 27 package dimensions 32 pin qfn, 7 x 7 mm mn suffix case 485j?02 issue c note 3 l d2 b 1 9 16 17 32 25 e2 32x 8 24 32x seating plane 0.15 c (a3) a a1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 2x k 8 4x top view side view bottom view exposed pad pin 1 location 0.15 c 2x e d a b 0.10 c 0.08 c c e 0.10 c 0.05 c a b e dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.250 0.250 0.350 d 7.00 bsc d2 5.160 5.260 5.360 e 7.00 bsc e2 5.160 5.260 5.360 e 0.650 bsc k 0.200 ??? ??? l 0.300 0.400 0.500
ncp5314 http://onsemi.com 28 package dimensions 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ?t? ?z? ?u? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t?u m 0.20 (0.008) z ac 32 lead lqfp case 873a?02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
ncp5314 http://onsemi.com 29 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 ncp5314/d v 2 is a trademark of switch power, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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